Integrated circuit devices, commonly known as chips, continue to become more powerful and complex as semiconductor manufacturing technologies have advanced. Whereas early integrated circuit devices included fewer than one hundred transistors, it is now common to integrate several million transistors into a single integrated circuit device. This increased transistor count enables some operations that once required several integrated circuit devices to now be implemented in a single integrated circuit device, often providing greater performance at a lower cost. For example, where previously a data processing system might require separate integrated circuit devices for a microprocessor, a memory, a bus interface, and a memory controller, advances in chip density now permit all of these functions to be integrated into the same integrated circuit device. Such devices are typically known as "systems on a chip" due to the high level of integration they provide.
Increases in chip density have also significantly affected the design methodology for integrated circuit chips. Rather than laying out individual transistors in a design, more complex devices are typically designed by assembling together multiple predefined "cells" of transistors that are obtained from a library, and that have previously been optimized and tested prior to use in the design. The functionality and complexity of individual cells continue to increase to the extent that particularly complex cells are often referred to as "embedded cores", or simply cores. Whereas many cells may represent relatively simple functions such as those of a logical AND gate or a multiplexer, a core typically represents a more complex function such as that of a processor, a controller, a memory, an interface circuit, or any other complex data processing circuit arrangement.
Another net effect of the increase in the complexity of integrated circuit devices is that testing of the manufactured devices has become significantly more complex and time consuming. For example, a device may be designed with a boundary scan architecture integrated therein with one or more serial chains of registers coupled to the I/O pins of a device. The registers in a serial chain, or scan path, are designed such that, when configured in a specific mode, the registers together operate as a shift register so that data may be shifted into the chain of registers from a single source to simulate different conditions, and so that data generated within a device may be shifted out through a single output. Thus, with a boundary scan architecture, the current state of various pins in a device at any given time may be recorded and later accessed via external equipment to verify the operation of a manufactured device.
In addition, built-in self-test (BIST) circuitry may also be incorporated into individual devices to perform predetermined testing operations, e.g., upon power-up of a device. For example, for logic devices such as processors and controllers, logical built-in self-test (LBIST) circuitry may be used to apply pseudo-random test patterns to logic gates to verify their correct operation.
Furthermore, beyond LBIST it may be desirable to access individual registers within an integrated circuit device during the functional mode of operation of the device to perform various service-related functions. For example, a standard interface, known as the Joint Test Action Group (JTAG) interface (IEEE Std. 1149.1) has been developed to facilitate external access to integrated circuit devices. With a JTAG-compatible integrated circuit device, a standardized test access port (TAP) is provided that permits boundary scan operations to be performed in response to commands issued by an external TAP controller through the TAP port of the device, with the results output back through the same port.
For each of these service and test-related operations, registers within an integrated circuit device are often grouped into serial scan chains, also referred to herein as scan ring segments. One or more interfaces, also referred to as scan interfaces, are typically provided to provide external access to the scan chains in an integrated circuit. Within such interfaces, one or more scan paths are defined, representing a data path beginning at an input port, through one or more scan chains, and terminating at an output port.
The number and length of scan chains, however, can vary significantly for any given integrated circuit design, e.g., based upon the number of registers to be scanned, the breakdown of registers based upon common functionality and/or clock domain, etc. Moreover, given that the registers of many integrated circuit designs may need to be accessed for multiple purposes, e.g., during testing of manufactured devices, during LBIST, and/or during performance of service-related functions while in functional modes of operation, etc., different combinations and/or numbers of scan chains may be optimal for different purposes. For example, where grouping one collection of registers into a scan chain may be optimal for LBIST, it may be optimal for service-related functions to group some of the registers in the collection in other scan chains.
Given the relatively large number of variables associated with grouping registers into one or more scan chains, a relatively large amount of custom logic is often required to provide a suitable scan interface with the registers in an integrated circuit design. Designing and verifying the operation of custom logic, however, can significantly impact the cost and development time for an integrated circuit. Moreover, when registers may need to be accessed for multiple purposes, multiple custom scan interfaces may also need to be developed, which only further increases the cost and effort associated with designing and verifying an integrated circuit design.
Therefore, a significant need exists for an improved manner of designing and providing access to registers arranged in scan chains within an integrated circuit device. Moreover, a significant need exists for an improved manner of optimizing the access to such registers for multiple purposes.